Seminar Short Report No
Seminar Short Report No.3
Student Name: Bhola
Student ID: 0680828
Venue: EC345, NCTU
Seminar: Design of Fault-Tolerant Neuromorphic Computing Systems
Date/Time: 10/9 Tuesday 10:30 ~ 12:00
Speaker: Dr. Krishneundu Chakrabarty,
Duke University ECE department chairman
Dr. Chakrabarty is now a professor and Chair of Electrical & Computer Engineering
department at Duke University. He is working currently on Neuromorphic computing
systems, anomaly detection, data & fault diagnosis, failure prediction and design for
testability of 3D SOC. He is a Chief Editor at IEEE Design & Test from 2010-2012,
and from 2012-2015 ACM Journal on Emerging Technology in Computing Systems
and presently he is Chief Editor of IEEE Transaction of VLSI Systems and also
associate editor of Biomedical Circuit systems, Multi scale computing systems and
Design Automation of Electronic systems.
What is Machine Learning? The definition is “Machine learning (ML) is a computer
based algorithm which can worked autonomously and collect data and their information
and help to improve current algorithm”. ML is an area of AI that can use statically
method to provide computer systems to able to learn from available data without
providing any explicitly programmed.
Also known as deep structured learning or hierarchical learning is type of a wide
descendant of machine learning technique can be supervised, semi
supervised or unsupervised. Deep learning is a part of machine learning learn at
multiple levels, Inspired by neuroscience, deep neural, recurrent neural, long short term
memory and convolutional neural network.
Motivation and Technology Overview:
PRAM cross bar:
Implement on vector matrix multiplication(I=VG), store G as a conductance matrix and
then apply V as input voltage to word lines.
Applications of PRAM:
In using neural network traning and Neural network inferencing.
PRAm is alwys prone to faults and basically four types of faults:
Hard- Unchangeable conductance.
Soft- Unchangeable but different conductance.
Static- Genrated during fabrication
Dynamic faults-Generated during read and write opearations.
It helps to mapping imrecise acuracy drop, yield of PRAM devices varies from 60% to
more than 90%.
Fault tolerent Framework for NN inference:
Mapping algorithm utilizing inherent fault tolerent capabilityof Neural Network to
minimize the effect of fault cells.
Redundant schemes and cuircuits are requred for furthre improvement fault tolerance.
In medical, In computer vision, Sppech recognition, Self driving vehicles, Robotics and
? How to detect Fault quickly? In online detection or block by block
? How to tolerate existing faults? Remapping- Match hard faults with inherent ‘0’s
? How to reduce the generation rate of new faults? Thersold training-To elminate
small magnitude write operations.
An RRAM based computing systems provides a promising solution Neuromorphic
RCS is vulnerable to faults:
? Fault tolerance designs are important for RCS
? Promising solutions have recently developed for faults tolerant in RCS
Better understanding of the physics of defects and the impact of faults on circuits